The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
As merely one example, scaling down of IC dimensions has been achieved by adoption of thinner photoresist films combined with a multilevel hardmask stack. For example, use of such a multilevel hardmask can be used to provide a desired aspect ratio at a desired resolution as part of a photolithography process. In various cases, the multilevel hardmask may include a carbon underlayer such as a spin-on-carbon (SOC) layer, upon which a silicon hardmask such as a spin-on-glass (SOG) layer may be deposited. A thin photoresist layer deposited on the silicon hardmask can be used to pattern the silicon hardmask (e.g., by an exposure, development, and etching process) Thereafter, the patterned silicon hardmask may be used to pattern the underlying SOC layer (e.g., by an etching process).
In various examples, however, deposition uniformity of the multilevel hardmask (e.g., SOC, SOG) is strongly related to the character of the substrate upon which it is being deposited. Moreover, advanced semiconductor processing technology employs a diverse array of processes and structures during a given manufacturing process. As such, at any given time during the semiconductor manufacturing process, a substrate surface may include any of a variety of material types (e.g., hydrophobic, hydrophilic, inert) and/or complex structures (e.g., 3-D FinFET structures, etc.) that exhibit distinct surface characteristics. Therefore, layers (e.g., SOC, SOG) spin-coated onto such diverse substrates may exhibit poor uniformity and poor planarization. Thus, existing techniques have not proved entirely satisfactory in all respects.